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Section 13.6 Summary

You will avoid a lot of debugging if you are careful to follow these VHDL guidelines:
  1. Always read the synthesis warnings and correct the problems they point to.
  2. Multiple drivers: Keep all assignments for a signal inside one process. Do not assign a signal in more than one process.
  3. Combinational loops: Rewrite them, or insert storage.
  4. Inferred latches: Make sure that every if-then has an else, and every case statement covers all possibilities or has a default (“when others =>”).
  5. Never gate the clock.
  6. Sensitivity lists: be sure to follow the rules, and obey the synthesis warnings.