Section 13.6 Summary
You will avoid a lot of debugging if you are careful to follow these VHDL guidelines:
- Always read the synthesis warnings and correct the problems they point to.
- Multiple drivers: Keep all assignments for a signal inside one process. Do not assign a signal in more than one process.
- Combinational loops: Rewrite them, or insert storage.
- Inferred latches: Make sure that every if-then has an else, and every case statement covers all possibilities or has a default (“when others =>”).
- Never gate the clock.
- Sensitivity lists: be sure to follow the rules, and obey the synthesis warnings.

