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Digital Electronics:
Supplement to Engs 31 / CoSc 56
Eric W. Hansen
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Front Matter
Colophon
Author Biography
Acknowledgements
I
Logic Design Basics
1
The World of 1s and 0s
1.1
Bits, codes, and numbers
1.2
Data bits and control bits
1.3
Operating on bits with truth tables
1.4
Operating on bits with logic equations
1.5
Electrical logic and logic diagrams
1.6
Implementing a logic circuit
2
Electronic Logic
2.1
Electric current and voltage
2.2
Electric circuits
2.3
Electronic switches (transistors)
2.4
Building gates from transistors
2.5
Electrical characteristics of logic circuits
2.6
Timing characteristics of logic circuits
2.7
Power consumption of logic circuits
2.8
Logic and voltage, again
3
Efficient Logic
3.1
Truth tables, again
3.2
Algebraic minimization
3.3
Karnaugh maps
3.4
DeMorgan’s Rules
3.5
Optimum minimization
4
Combinational Logic
4.1
Multiplexers
4.2
One-hot decoders
4.3
Seven-segment display decoder
4.4
Encoders
4.5
Lookup tables
II
VHDL-based design
5
Top level modeling with VHDL
5.1
Preview of (more) modern logic design
5.2
Input and output ports (entity block)
5.2
Exercises
5.3
Internal logic (architecture block)
5.3
Exercises
6
VHDL processes
6.1
Events
6.2
Processes
6.3
Sequential statements in processes
6.3
Exercises
6.4
If-then-else statements
6.5
Case statements
6.5
Exercises
7
Simulating VHDL models
7.1
Introduction
7.2
VHDL testbench structure
7.3
Simulating with EDA Playground
7.3
Exercises
7.4
Simulating with Xilinx Vivado
8
Modeling synchronous systems
8.1
VHDL flip-flop model
8.1
Exercises
8.2
Registers
8.3
Counters
8.3
Exercises
8.4
Testbenches for synchronous systems
9
Modeling mixed synchronous-asynchronous systems
9.1
Flip-flop model with asynchronous controls
9.1
Exercises
9.2
Counters with terminal count output
9.2
Exercises
9.3
A template for mixed synchronous and asynchronous processes
10
Counters
10.1
Overview of simple counters
10.2
Counter controls
10.2
Exercises
10.3
Clock dividers
10.3
Exercises
10.4
Counter with variable step size
10.4
Exercises
11
Synthesis and implementation
11.1
Programmable logic
11.2
Mapping ports to pins
11.3
Logic synthesis for FPGAs
11.4
Logic implementation on FPGAs
11.5
Physical testing
12
State machines in VHDL
12.1
State machines
12.2
VHDL template for state machines
12.3
Simulating state machines
12.4
State machine synthesis
13
VHDL modeling pitfalls
13.1
Multiple drivers
13.2
Combinational loops
13.3
Inferred latches
13.4
Gated clocks
13.5
Incomplete sensitivity lists
13.6
Summary
14
Scalable VHDL models
14.1
Parametrized designs
14.2
Computed parameters
14.3
Counters: integer or unsigned?
III
Components and Subsystems
15
Subsystem design
15.1
System architecture
15.2
Register transfer level (RTL)
15.3
Structural VHDL
15.4
Parametrized components: generics
16
Multiplexed seven-segment display
16.1
Seven-segment displays
16.2
Multi-digit display
16.3
Multiplexed display driver
16.3
Exercises
17
Shift registers
17.1
Shift register logic
17.2
VHDL models for shift registers
17.2
Exercises
17.3
Serial communication
18
Asynchronous serial communication (UART)
18.1
Serial communication
18.2
UART protocol
18.3
UART system design
18.3
Exercises
18.4
The RS-232 standard
19
Serial Peripheral Interface (SPI)
19.1
Serial communication
19.2
SPI protocol
19.3
SPI interface design
19.3
Exercises
20
Video graphics (VGA)
20.1
Digital images
20.2
VGA image displays
20.3
VGA interface: Controller
20.4
VGA interface: Datapath
20.5
Moving objects and simple games
20.6
Streamlining VGA arithmetic
Backmatter
References
Index
Colophon
Section
20.6
Streamlining VGA arithmetic
Managing bricks, checking interiors...
