Sequential statements in processes

Section 6.3 Sequential statements in processes

A VHDL model is a collection of concurrent processes. So far, we have used processses to represent individual logic gates. It must be stressed that this is only illustrative. One would rarely, in practice, use this apparatus to model something as simple as a logic gate. For the two-input multiplexer we have been considering, the single equation y <= (not(s) and A) or (S and B); is far more compact. However, as we proceed we’ll gradually approach situations where we can see the superiority of concurrent process models.

First of all, processes may contain multiple statements. For example, the multiplexer architecture may be written

architecture gatelevel of mux2to1 is
          signal asn, bs: std_logic;      -- intermediate nets
      begin

      process(A, B, S, asn, bs)           
         begin
            asn <= not(S) and A;   -- 1
            bs <= S and B;         -- 2
            y <= asn or bs;        -- 3	 
      end process;

      end gatelevel;

with the equations for all three gates in one process. The execution sequence for this process is a more complicated than we’ve seen, so we will take it a step at a time. Suppose \(S=0\) and the A port changes value. The following cascade of events and process activations ensues:

The event on A activates the process. The three statements are evaluated, in order, using the values that are in effect at the time of activation. In Statement 1, a new value for asn is scheduled, but not assigned. In Statement 2, the scheduled value of bs is unchanged, because neither S nor B changed. In Statement 3, the scheduled value of y is also unchanged, because the new value of asn has not yet been assigned, only scheduled. Statement 3 is still working with the old values.
When the end of the process is reached, the scheduled values are assigned; asn receives its new value. The process then suspends, pending a new event.
Because asn changed, there is an event, and the process activates. The three statements are evaluated, in order, using the current values. This time, y will receive a new scheduled value.
The scheduled values are assigned, and the process suspends, pending further events.

The result, after two activations of the process, is that y is updated with the new value of A. If you compare this with the logic diagram, Figure 5.3.3, you will see that it matches the way one gate drives another.

Checkpoint 6.3.1.

Walk through the activations of the process following a change in S from 0 to 1. Compare with the flow of signals in time through the logic diagram.

In a conventional programming language, if you had two statements like this:

y = a;
y = b;

you would see y change twice. First, y would take the value of a, then it would take the value of b. In VHDL, if you wrote an architecture like this:

architecture gatelevel of foo is
begin
   y <= a;
   y <= b;
end gatelevel;

The port y would concurrently be assigned a and b. This is a “multiple driver error”, like wiring two gate outputs to the same gate input. On the other hand, if these statements are placed inside a process,

architecture gatelevel of foo is
begin
   process(a,b)
   begin
      y <= a;   -- 1
      y <= b;   -- 2
    end process;
end gatelevel;

execution proceeds as follows, in response to an event on one of the inputs:

The process activates, and Statement 1 is evaluated. The value of y is scheduled to be the value of a, but as usual, it is not to be assigned until the process suspends.
Statement 2 is evaluated. The value of y is now scheduled to be the value of b, overriding the previously scheduled assignment.
y is assigned its new value, and the process suspends pending further events.

There is no multiple driver error. And unlike the conventional programming language, y is only assigned once. This feature permits more sophisticated logic to be placed inside processes.

Exercises Exercises

Here is a good place to pause and do some practice problems...

1.

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