Electrical logic and logic diagrams

Section 1.5 Electrical logic and logic diagrams

Truth tables and logic equations are mathematical descriptions. To actually build a digital processor, we must physically represent the 1s and 0s and the logical operations.

The logical operations AND, OR, and NOT are realized by electronic circuits called logic gates. A network of logic gates, interconnected by wires, is called a logic circuit, represented graphically by a logic diagram, Figure 1.5.1. The logical values (1s and 0s) carried by the wires are referred to as logic signals. In digital electronics, logic signals are represented by HIGH and LOW voltage levels. Commonly, LOW is about 0.5V and HIGH is about 3V. The usual voltage-logic pairing is HIGH with TRUE and LOW with FALSE, although there are occasions when it is useful to reverse the pairings (LOW with TRUE and HIGH with FALSE).

Figure 1.5.1. A logic diagram, using AND, OR, and NOT gate symbols.

Each type of gate has a distinct symbol, as noted in the figure. AND gates and OR gates may have any number of inputs, but each may have only one output. The NOT gate, or inverter, always has only one input and one output. The number of inputs a gate has is called its fan-in. A signal connected to the input of a gate or to a system output is called the driver for that input or output.

By convention, logic diagrams are drawn with system inputs, also called input ports, on the left and system outputs (output ports) on the right. We imagine the logic signals to be flowing from the inputs through the gates to the outputs. As much as possible, logic gates are oriented with their outputs pointing to the right. Paths (wires) that intersect are marked with a dot at the intersection. Non-intersecting wires merely cross.

The process of translating a logic equation into a logic diagram or circuit is called logic synthesis. The following design rules must be obeyed when synthesizing logic circuits. When you have drawn a logic diagram, check it against these design rules. If you discover any errors, go back and examine your design process to see what went wrong, and correct the errors.

Each input of a gate may have only one driver. Each gate input is connected either to one (and only one) input port or to one (and only one) output of another gate.
A gate may not drive itself. The output of a gate may not be connected back to an input of the same gate.
Every gate output may be connected to (fan out to) an output port or to one or more inputs of other gates.
Two gate outputs may not be connected together.

Example 1.5.2.

The logic equation for the two-bit compararison \(x \gt y\) (Checkpoint 1.3.4)is

\begin{equation*} g = {x_1}^\prime \cdot x_0 + x_1 \cdot {x_0}^\prime \cdot {y_1}^\prime + x_1 \cdot x_0 \cdot y_1 \cdot {y_0}^\prime. \end{equation*}

The logic diagram is shown below

Logic diagram with AND, OR, and NOT gate symbols wired together.

The circuit has four NOT gates, one each of two, three, and four-input AND gates, and a three-input OR gate. Verify for yourself that the circuit obeys the design rules.

Practice.

Make logic diagrams from the logic equations derived in previous checkpoints. Check your circuits against the design rules.

Checkpoint 1.5.3.

Two-bit odd number detector

\begin{equation*} y = {x_1}^\prime \cdot x_0 + x_1 \cdot x_0 \end{equation*}

Checkpoint 1.5.4.

One-hot decoder.

\begin{align*} y_0 \amp= {n_1}^\prime \cdot {n_0}^\prime \\ y_1 \amp= {n_1}^\prime \cdot n_0 \\ y_2 \amp= n_1 \cdot {n_0}^\prime \\ y_3 \amp= n_1 \cdot n_0 \end{align*}

Checkpoint 1.5.5.

Two-input multiplexer

\begin{equation*} y = S^\prime \cdot A + S \cdot B \end{equation*}

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