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Digital Electronics: Supplement to Engs 31 / CoSc 56

Eric W. Hansen

Section 11.3 Logic synthesis for FPGAs

The translation of a VHDL model into an FPGA prototype occurs in two steps: synthesis and immplementation. In logic synthesis, the EDA tool analyzes the VHDL source code to identify the logical resources needed by the prototype. For example, a simple four-bit binary counter contains the process:
process(clk)
begin
   if rising_edge(clk) then
      uX <= uX+1;           -- uX is unsigned(3 downto 0)
   end if;
end process;

X <= std_logic_vector(uX);  -- map to output port
The synthesis tool infers from this statement that a four-bit register is required to hold uX, and an incrementer is needed to update the count. A netlist is created from this decomposition, which can be displayed as a schematic diagram.
described in detail following the image
Figure 11.3.1. Schematic diagram elaborated from the VHDL model for a four-bit counter. The counter consists of a register and an incrementer.
The register, in turn, is decomposed into four flip-flops and the incrementer is decomposed into four lookup tables.
described in detail following the image
Figure 11.3.2. Schematic diagram synthesized from VHDL model for a four-bit counter. There are four flip-flops for the counter state and four LUTs for the next-state logic (incrementer). The label “FDRE” denotes a D flip-flop with reset and enable, one of several types of flip-flop that can be synthesized in this FPGA [21].
The Xilinx Vivado tool, which we use in this class, also makes the netlist available in tabular form, with hyperlinking between the table and the schematic:
described in detail following the image
Figure 11.3.3. Schematic diagram and netlist synthesized from the VHDL model for the four-bit counter. Clicking a net in the netlist highlights the net in the schematic, and vice-versa.
Additionally, the tool enables the designer to peek inside the LUTs to see their truth tables:
described in detail following the image
Figure 11.3.4. Schematic diagram and netlist synthesized from the VHDL model for the four-bit counter. Double-clicking a LUT in the schematic reveals its truth table. The truth table shown implements a two-input exclusive-OR function.
Compare this with logic synthesis for a breadboarded prototype, in which the designer analyzes the logic diagram to determine an effective set of IC packages, then makes a netlist in tabular form or by annotating the logic diagram.
During synthesis, the EDA tool will note syntax errors in the VHDL, issue warnings (e.g., Chapter 13), and report other useful information like estimates of propagation delays and resource usage.
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