Digital Electronics: Supplement to Engs 31 / CoSc 56

See Section 8.1.

When modeling any clocked circuit (flip-flop, register, etc), do not include a clock enable (CE) control by writing if rising_edge(clk) and (CE='1') then.... While it is logically equivalent to the nested if statements, it implies that the clock is ANDed with the enable signal, making a gated clock. After simulation, when the VHDL model is synthesized to a circuit, an intervening AND gate will cause the flip-flop’s clock to be delayed, potentially introducing timing errors.

The correct way to include a clock enable is shown in Listing 8.1.2. And, in general, the VHDL model for a synchronous system must always be of the form:

if rising_edge(clk) then
   -- Everything else
end if;

That said, clock gating is often used in digital systems, especially microcontrollers, to reduce power consumption and extend battery life. When a subsystem is not being used, it can be “put to sleep” by stopping its clock. This requires additional control circuitry to know when to start and stop the clock, and careful design to avoid timing errors between subsystems.