VHDL flip-flop model

Section 8.1 VHDL flip-flop model

The basic D flip-flop changes its state in response to the rising edge of a clock signal. This is modeled with a process, like this:

process(clk)                   -- 1
begin
   if rising_edge(clk) then    -- 2, 5
      Q <= D;                  -- 3
   end if;
end process;                   -- 4, 6

Listing 8.1.1. Basic process for an edge-triggered flip flop. Comments are keyed to the explanation in the text.

Let’s walk through the operation of this process and see how it models the operation of a flip-flop:

The process is sensitive only to the clk> input. Between events on clk (edges), the process is suspended. The D input relies on a rising clock edge; it cannot, on its own, effect a change in the state of the flip-flop.
On a rising clock edge, the process activates. Inside, if rising_edge(clk) checks if the event is a rising edge or a falling edge. A rising edge allows the next statement, Q <= D;, to be evaluated.
The assignment of D to Q is scheduled.
When the end of the process is reached, Q is assigned and the process suspends.
Later, the clock has a falling edge. This event also activates the process. However, because the event is a falling edge, the rising_edge(clk) function returns FALSE. The assignment statement Q <= D; is not evaluated.
At the end of the process, no change is made to to Q. The process idles, pending the next clock event.

This basic template can be embellished in several ways to add features. For example, here is a model for a flip-flop with enable:

process(clk)                   
begin
   if rising_edge(clk) then    
      if CE = '1' then
         Q <= D; 
      end if;                 
   end if;
end process;

Listing 8.1.2. VHDL model for an enabled edge-triggered flip flop.

In this model, the rising clock edge allows the inner if-then to be evaluated. Then, if en is TRUE, Q is updated. Otherwise, an assignment of Q is not made, and the flip-flop holds its state.

Do not write if rising_edge(clk) and (CE='1') then.... While it is logically equivalent to the nested if statements, it implies that the clock is ANDed with the enable signal, making a gated clock. After simulation, when the VHDL model is synthesized to a circuit, an intervening AND gate will cause the flip-flop’s clock to be delayed, potentially introducing timing errors. The correct way is shown in Listing 8.1.2. In general, the VHDL model for a synchronous system must always be of the form:

if rising_edge(clk) then
   -- Everything else
end if;

Checkpoint 8.1.3.

Write a VHDL model for an edge-triggered flip-flop with synchronous reset.

Answer.

process(clk)                   
begin
   if rising_edge(clk) then    
      if reset = '1' then
         Q <= '0';
      else
         Q <= D; 
      end if;                 
   end if;
end process;

Listing 8.1.4. VHDL model for an edge-triggered flip flop with synchronous reset.

In the solution of preceding exercise, Listing 8.1.4, the reset function is the first to be evaluated, in keeping with the usual priority of reset over loading. In principle, one could also write the model like this:

process(clk)                   
begin
   if rising_edge(clk) then    
      Q <= D; 
      if reset='1' then
         Q <= '0'; 
      end if;                 
   end if;
end process;

or even this:

process(clk)                   
begin
   if rising_edge(clk) then   
      Q <= '0';
      if reset='0' then
         Q <= D; 
      end if;                 
   end if;
end process;

However, neither of these, in my opinion, is as clear as the original solution in expressing the priority of reset over load. Always strive for readable code.

Exercises Exercises

1. Flip-flop with two controls.

Write a VHDL model for an edge-triggered flip-flop with synchronous enable and reset controls. Reset has priority over enable.

Answer.

process(clk)                   
begin
   if rising_edge(clk) then    
      if reset = '1' then
         Q <= '0';
      elsif CE = '1' then
         Q <= D; 
      end if;                 
   end if;
end process;

Listing 8.1.5. VHDL model for an edge-triggered flip flop with synchronous reset and enable.

Note how the nested if-then statements express the priority of reset over enable.

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