Digital Electronics: Supplement to Engs 31 / CoSc 56

The simplest counter is just a register and an incrementer. On each rising clock edge, the count advances, and when it reaches the capacity of the register (\(2^N-1\) for an \(N\)-bit counter), on the next edge the count resets (or “rolls over”) naturally to zero. Control inputs modify this natural sequence, e.g., by halting the count (enable) or forcing it to zero (clear). In this course, all counter controls are designed to be synchronous, acting on the rising clock edge. They are never asynchronous.

When there is more than one control input, the designer must decide how to prioritize them. Typically, the clear function has the highest priority, followed by the enable. These functions are often built into the register itself. In hardware, the priority of control signals is expressed through a sequence of multiplexers, with the highest priority control placed closest to the register Figure 10.2.1

The clear-over-enable priority is modeled in VHDL by nested if-then-else statements.

-- Signal X is previously declared as unsigned; all other signals are std_logic

   process(clk)                       
   begin
      if rising_edge(clk) then
         if CLR = '1' then                -- 1
            X <= (others => '0');         -- 2
         elsif EN = '1' then              -- 3
            X <= X+1;                  
         end if;                          
      end if;                             -- 4
   end process;

Watch the following video for more about nested control statements.

-- Signals X and D are previously declared as unsigned;
-- all other signals are std_logic.

   process(clk)                       
   begin
      if rising_edge(clk) then
         if LOAD = '1' then                
            X <= D;         
         else            
            X <= X+1;                  
         end if; 
      end if;                         
   end process;