Simulating with Xilinx Vivado

Section 7.4 Simulating with Xilinx Vivado

Here is a video showing how to get started with the Vivado simulator:

In both the Vivado simulator and in EDA Playground, errors are indicated by changing the color of the waveform and also by labeling the logic value something other than ’0’ or ’1’. VHDL, as a language originally developed for modeling and simulation, actually defines nine possible values for a signal or port of type std_logic. The most important ones for us, so far, are:

’U’: Uninitialized. When a signal is declared, it has this value until it is assigned ’1’ or ’0’.
’X’: Unknown. The simulator is unable to figure out what value to assign. This happen, for instance, if you try to operate on an uninitialized signal. If a signal A is uninitialized, then y <= A and B; will return ’X’ for y. Many “red X errors” can be avoided by being careful to initialize all the signals in an architecture, e.g., signal A: std_logic := '0';.
’0’: Logic 0
’1’: Logic 1

With experience, you will learn to trace occurrences of ’U’ and ’X’ back from a simulation to the coding error that produced them, and make the necessary corrections.

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