1.
Following the ideas described above, design the block diagram for a four-digit multiplexed display driver. Your available components are a single-digit decoder, counter, one-hot decoder, and multiplexer(s).
Section 16.3 Multiplexed display driver
A number is displayed on a digit by pulling one of AN0-AN3 LOW, and also pulling appropriate cathodes LOW. For example, to display the number 3 on Digit 2, pull AN2 LOW, and pull cathodes CA, CB, CC, CD, and CG LOW.
A four-digit number is displayed one digit at a time. Each digit is four bits, hexadecimal 0 through F. The logic selects one of the four-bit numbers in turn, converts it to seven segments with a combinational hex-to-seven-segment decoder, which is connected to the display, CA-CG. In synchrony with the digit selection, the appropriate anode (AN0-AN3) is activated. Then the next number is selected and displayed, and the next, cycling through the four numbers rapidly enough that the flashing digits appear to be on simultaneously. Sixty hertz is a good cycle rate to avoid perceptible flicker in the entire display. The display must move from digit to digit at four times that rate, or 240 Hz. This is demonstrated in the video, Figure 16.3.1.
A multiplexed seven-segment display driver is a useful component to have in your personal parts library. You can pull it out and add it to a design whenever needed.
Exercises Exercises
2.
Write a VHDL model (entity and architecture) for a multiplexed dislay driver component.
3.
Modify your block diagram and VHDL model with an additional control signal, BLANK. When BLANK is asserted, leading zeros are suppressed, i.e., "0070" is displayed as " 70".
