Digital Electronics: Supplement to Engs 31 / CoSc 56

Capturing a design with a hardware description language enables the designer to then test the design, by simulation, before implementing it. It is easier, and less expensive, to debug a design in simulation rather than discovering design errors in hardware. Simulation does not remove the need for physical test, especially in this class, but it will get you closer to a correct design.

Prior to the advent of simulation, physical test looked like Figure 7.1.1. A design, captured in a logic diagram, was prototyped on a hand-wired circuit board. Stimuli (inputs) were supplied by switches, function generators, or other digital subsystems. Of course, there would be bugs—logic errors or wiring errors. Debugging was carried out by probing signals of interest with an oscilloscope or a more powerful tool called a logic analyzer, and deducing causes from the observed waveforms. The circuit would be rewired to correct the error, and the process would repeat until all the bugs were fixed.

Test by simulation is similar in spirit, as shown in Figure 7.1.2, below. The prototype system, whether hardware or VHDL model, is called the device under test (DUT) or unit under test (UUT). Physical stimuli from a function generator or switches are replaced by an additional VHDL model called a testbench. The testbench generates an appropriate sequence of stimuli and applies them to the input ports of the UUT. The role of the oscilloscope or logic analyzer in displaying the outputs of the UUT is played by additional software that can display signals in the UUT model as waveforms on a screen. The simulator is usually able to watch not just the model’s output ports, but also its internal signals. It is also possible to write a testbench in such a way that it not only generates stimuli but also compares the outputs with known correct responses to the stimuli. We shall use only waveform observation in this class.