Serial communication

Section 19.1 Serial communication

Chapter 18 introduced serial communications and the two problems that must be solved in any serial link design (Figure 19.1.1):

The receiver’s serial-to-parallel register must shift at the proper times, once per bit, and safely within each bit.
The receiver must know when a new packet is arriving, so that the stream is properly framed into bytes.

described in detail following the image — Figure 19.1.1. Serial data communication. A block (e.g., a byte) of parallel data is serialized and transmitted as a bit stream over a single wire. In some protocols, additional wires carry timing signals to synchronize the receiver with the transmitter. The received bit stream is deserialized and output as parallel data.

In the UART protocol for asynchronous serial communication, the synchronization is embedded in the data stream (Section 18.2). In this chapter we will see a different approach, a synchronous protocol called the Serial Peripheral Interface (SPI) bus. It solves the synchronization problem by sending a clock signal and a framing signal alongside two (transmit and receive) data lines. A state machine in the transmitter generates the timing signals, and a state machine in the receiver uses the timing signals to control the receiver’s shift register.

The SPI bus is used for package-to-package communication on a single circuit board. It is capable of full duplex (bidirectional) communication at high speeds, up to 10 million bits per second. Many of the peripheral modules, or Pmods

store.digilentinc.com/by-communication-protocol/spi/

, available for the Digilent FPGA development boards use a SPI interface.

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