Digital Electronics: Supplement to Engs 31 / CoSc 56

Referring again to the counter, parameters REGSIZE and MAXVAL are closely connected, since MAXVAL cannot exceed the largest number held in the register, which is 2\(^\text{REGSIZE}-\)1. Solving this inequality for REGSIZE, we obtain REGSIZE \(\ge\) log\(_2\)(MAXVAL\(+\)1). Thus, if we begin with MAXVAL, we can calculate the minimum required REGSIZE by rounding log\(_2\)(MAXVAL\(+\)1) up to the next integer. For example, for MAXVAL=9, we calculate log\(_2\)(10) = 3.32; rounding up gives 4, as expected. For MAXVAL=23, log\(_2\)(24) = 4.59, which rounds up to 5.

VHDL has a library, ieee.math_real, that enables us to make this calculation in the architecture. The functions in this library are not synthesizable in hardware, but they can be used to do arithmetic on parameters during simulation or synthesis. The math_real library can also be used to compute more complex stimuli, such as sine waves, in a testbench. All the available functions in the math_real library are helpfully described in References [1], pp 443ff, and [15].

Here is how to write the calculation of REGSIZE from MAXVAL:

--  Include the math_real library
    use ieee.math_real.all;

--  In the architecture
architecture behavior of example is
    constant MAXVAL: integer := 9;   -- maximum count
    constant REGSIZE: integer := integer( ceil( log2 ( real(MAXVAL+1) )));
    ...

This video presents another common example of a parametrized architecture: