Chapter 9 Modeling mixed synchronous-asynchronous systems
A purely combinational circuit like a multiplexer or decoder is modeled by a VHDL process that sensitive to all the circuit’s inputs. The circuit responds immediately (after a propagation delay) to changes in its inputs. A system like this, which operates without a clock, is said to be asynchronous. On the other hand, the flip-flops, registers, and counters we have seen so far respond only to clock edges. Their other inputs, like data (D) or enable (CE), do not have the ability to activate the circuit. Systems like these, whose activations are synchronized to a clock, are called synchronous.
There are also systems that have both synchronous and asynchronous parts. This chapter is about how to model such mixed circuits in VHDL.
