Section 13.1 Multiple drivers
You know that in hardware, an input to a logic circuit (gate, flip-flop, multiplexer, etc) may have only one driver, either a system input port or the output of another logic circuit within the system. If an input is wired with multiple drivers, the drivers will “fight” each other electrically, giving an indeterminate voltage level at the input and/or causing excessive current flow in the drivers leading to a burned-out chip.
In VHDL, as in hardware, multiple drivers are not allowed. As noted earlier, in Section 6.3, you cannot have two concurrent statements, or processes, driving the same signal. The following is allowed:
process(a, b)
begin
y <= a;
y <= b;
end process;
because the two assignments are inside a process, and evaluated in order, with the final value of
y assigned at the end of the process. But this is not allowed:process(a)
begin
y <= a;
end process;
process(b)
begin
y <= b;
end process;
The two processes concurrently attempt to assign a value to
y. The simulator will not be able to resolve the conflict and an error will be thrown.A very common instance of the multiple driver error occurs when resetting a counter:
process(a)
begin
if a='1' then
x <= "0000";
-- other logic
else
-- other logic
end if;
end process;
process(clk)
begin
x <= x+1;
end process;
The designer’s intent here is to use the input
a to reset the counter and to control other functions. But, by assigning x in both processes, x has been given two drivers. The correct way to write this is to put the reset function into the counter’s process and leave the other logic as-is:process(a)
begin
if a='1' then
-- other logic
else
-- other logic
end if;
end process;
process(clk)
begin
if a='1' then
x <= "0000";
else
x <= x+1;
end if;
end process;
Now all the assignments to
x occur in the same process, and x has only one driver.
