Simulating state machines

Section 12.3 Simulating state machines

The key point in simulating a state machine in VHDL is to write a stimulus process that asserts the inputs so that all state transitions can be tested. The testbench must do this without explicit knowledge of what state the system is in. Its knowledge of the state machine is restricted to the outputs, and its influence on the state machine is solely through the inputs. For example, here is a stimulus process for the state machine in Listing 12.2.1.

stim_proc: process
begin
    go <= '0';  wait for 4*CLK_PERIOD;  -- Wait in idle state for a while

    go <= '1';  wait for 4*CLK_PERIOD;  -- Watch the green light flash

    go <= '0';  wait for 4*CLK_PERIOD;  -- Give it time to get back to idle

    go <= '1';  wait for 5*CLK_PERIOD;  -- Odd number of clock periods this time

    go <= '0';  wait for 4*CLK_PERIOD;  -- Back to the idle state

    wait;                                  -- All done
end process stim_proc;

Here is a simulation with EDA Playground

www.edaplayground.com/x/26S4

. EDA Playground does not show the states in a VHDL simulation. Because of this, you are advised to use Vivado instead from now on. It is very difficult to debug a state machine without direct knowledge of what state you are in!

described in detail following the image — Figure 12.3.1. Waveform generated by EDA Playground simulation of Listing 12.2.1. The waveform does not display the states, only the inputs and outputs. (Right-click “View image” (Firefox) or Right-click “Open image in new window” (Safari) to enlarge the image.)

Here is the same simulation, performed with Vivado. By showing the states as well as the inputs and outputs, it is easier to compare the simulation with the state diagram.

Prev Top Next