Digital Electronics: Supplement to Engs 31 / CoSc 56

As a general rule, any digital processor will have a datapath and a controller Section 1.2. This is certainly true of the core processor for a large system, and many subsystems and I/O interfaces are themselves processing units with their own datapaths and controllers.

In this class we adopt a common datapath methodology called register transfer level (RTL) design. The layout of an RTL module is shown in Figure 15.2.1. This is a good design pattern to follow for any module of a digital design. Beginning at the boundary of the module, input data is received and stored in an input register. The module’s output data is stored in an output register. Between these registers, the module’s datapath processes the input data and produces the output data. The input, output, and datapath registers are controlled by signals generated by the module’s controller, which is a state machine. The controller also receives control signals from other modules that source data, and outputs control signals to modules that receive data. Like most general block diagrams, this seems complicated at first, but will become clear as we work through several concrete examples in subsequent chapters.

The functionality of the datapath is organized as a set of register transfers, each consisting of one or more source registers, a block of combinational logic that operates on the data, and a destination register to store the result, Figure 15.2.2. Registers in an RTL design almost always are equipped with enable inputs to control whether the register updates, performing the operation, or holds. Optionally, they may also have clear inputs.

To make this a little more concrete, Figure 15.2.3 shows three common register transfer operations.

In the incrementer, the source and destination are the same register. The combinational logic adds 1 to X, and the result is written back into X on the rising edge of the clock if ENx is TRUE. The VHDL model for this RTL is:

if rising_edge(clk) then
   if ENx = '1' then
      X <= X+1;
   end if;
end if;

In the accumulator, the X and Y registers are both sources, and the Y register is also the destination. The combinational logic is an adder, calculating the sum of X and Y, which is then loaded back into Y on the rising clock edge if ENy is TRUE. If values \(x_1, x_2, ... \) are sequentially stored in X, after N clock cycles the Y register holds the accumulated sum \(x_1 + x_2 + ... + x_N\text{.}\) The Y register can be cleared as well as enabled; as usual, we assume that in the physical register, clear has priority over enable. The VHDL model for this RTL is:

if rising_edge(clk) then
   if CLRy = '1' then
      Y <= (others=>'0');
   elsif ENy = '1' then
      Y <= Y + X;
   end if;
end if;

Loading the X register is a separate register transfer, controlled by the ENx input.

In the third example, there are two source registers, A and B, and one destination register, Y. Again, the combinational logic is an adder, calculating the sum of A and B. The sum is stored back into Y on the rising edge of the clock, if ENy is TRUE. The VHDL model for this RTL is:

if rising_edge(clk) then
   if ENy = '1' then
      Y <= A + B;
   end if;
end if;

Loading A and B are also register transfers, controlled by ENa and ENb, respectively.

The control inputs -- enable and clear -- for the registers are connected to the controller. The state machine is then designed so that it asserts the control signals in the right order to load the source and destination registers and correctly sequence the datapath’s RTL operations.

Again, don’t worry if this feels very abstract at this point. As we go through different subsystem designs in the coming chapters, watch for the register transfer operations and how the controllers are designed. Your understanding will increase as you see examples and also begin to design your own subsystems in lab.