Digital Electronics: Supplement to Engs 31 / CoSc 56

Recall that the parallel-in, parallel-out register is modeled by a VHDL process, like this:

-- x and y are vector signals of the same type and size
process(clk)
begin
    if rising_edge(clk) then
       if clear='1' then
          y <= (others=>'0');
       elsif load='1' then
          y <= x;
       end if;
    end if;
end process;

The four-bit parallel-in, serial-out register in Figure 17.1.2 could be modeled like this, continuing to use y to denote the contents of the register.

-- x and y are four-bit vector signals
serial_out <= y(0);
process(clk)
begin
    if rising_edge(clk) then
       if load='1' then
          y <= x;
       else
          y(3) <= serial_in;
          y(2) <= y(3);
          y(1) <= y(2);
          y(0) <= y(1);
       end if;
    end if;
end process;

This is logically correct, but it rapidly becomes unwieldy for modeling large registers. A compact way of writing the same model is like this:

-- x and y are four-bit vector signals
serial_out <= y(0);
process(clk)
begin
   if rising_edge(clk) then
      if load='1' then
         y <= x;
      else
         y <= serial_in & y(3 downto 1);
      end if;
   end if;
end process;

This model introduces a new VHDL language feature, the concatenation operator, &. The expression serial_in & y(3 downto 1); says that the serial_in bit is concatenated with the upper three bits of y, making a new vector with serial_in in the most-significant place and y(1) in the least-significant place. Then, the assignment of this new vector to y on the rising clock edge causes the contents of the register to be replaced by this new vector, i.e., the register has been shifted. This construction is easily expanded to longer registers simply by changing the upper index of y, e.g., from 3 to 7, 15, 31, etc.

This video complements the material presented so far: