Clock dividers

Section 10.3 Clock dividers

A counter with maximum count \(M-1\) and a terminal count output, TC, counts in the sequence \(0, 1, 2, ..., M-1, 0, ...\) and asserts TC once every \(M\) clock cycles. The period of the TC signal is \(M\) times the clock period, and its frequency is \(1/M\) times the clock frequency. This property can be used to make a slower clock signal, e.g., converting a 100 MHz clock to 1 MHz. A circuit which performs this function is called a clock divider.

A clock signal is usually required to have a 50% duty cycle, that is, it is HIGH for 50% of its period and LOW for the other half-period. The TC output of a counter has a lower duty cycle, because it is only asserted for one clock cycle out of \(M\text{.}\) We cannot just use the TC output as a clock. To obtain a 50% duty cycle output, we use the setup shown in Figure 10.3.1.

described in detail following the image — Figure 10.3.1. Clock divider constructed from a counter and a toggle flip-flop (T-flop). The frequency of the slow_clock signal is 1/M the frequency of the master clock, and it has a 50% duty cycle.

The toggle flip-flop, or T-flop, is enabled by its T input. When T is TRUE, the T-flop changes its state from 0 to 1 or from 1 to 0 on every rising clock edge. When T is FALSE, the T-flop holds its state. In this circuit, the counter is designed to assert TC every \(M/2\) clock cycles (\(M\) must be even). For one clock cycle out of every \(M/2\text{,}\) TC is asserted and the T-flop toggles. Thus, the T-flop’s output is 1 for \(M/2\) clock cycles and 0 for \(M/2\) clock cycles. It has a frequency of \(1/M\) times the original clock frequency, and its duty cycle is 50%.

The VHDL model for the clock divider process is given below. Compare with Listing 9.2.3.

-- Signal X is previously declared as unsigned.
-- Constant M is declared as an integer, intialized to an even number.
-- Signal slow_clock is std_logic, initialized to '0'

   clock_divider: process(clk)                       
   begin
      if rising_edge(clk) then
         if X = M/2-1 then                     -- 1            
            X <= (others => '0');              -- 2
            slow_clock <= not(slow_clock);     -- 3        
         else            
            X <= X+1;                          -- 4                 
         end if; 
      end if;                         
   end process clock_divider;

Listing 10.3.2. VHDL model for a \(1/M\) clock divider with 50% duty cycle output. Comments are keyed to explanations in the text.

Note the following about the VHDL model:

The numeric_std library, which is included whenever there is arithmetic, allows an unsigned to be compared with an integer. During synthesis, the integer quotient M/2 is computed and the result is “hardwired” into the synthesized hardware.
The VHDL construct (others => '0') makes a bit vector "0...0" that matches the length of X.
The slow_clock signal is toggled every \(M/2\) clock cycles. This line results in the synthesis of the T-flop from a D-flip and an inverter.
If X is not at its terminal count, it is incremented at every rising edge.

Exercises Exercises

1. Sizing a clock divider.

What is the minimum size, in bits, of the register in a clock divider that reduces a clock from 100MHz to 1MHz?

2. Clock divider simulation.

Expand the clock divider process, Listing 10.3.2, to a full VHDL entity and architecture (I suggest \(M=6\) for compactness), write a testbench, and simulate.

3. Alternative clock divider.

Design a clock divider using a \(\div M\) counter and a comparison operation (\(=, \, \gt, \, \lt, \,...\)). Which design do you prefer, and why?

Answer.

The counter runs from 0 to M-1. The count X is compared with the constant M/2. If X < M/2, the slow_clock output is asserted. Otherwise, slow_clock is 0.

Both designs require the same number of flip-flops. The second design requires an extra comparator to produce the slow_clock signal. Thus, the first design may be more efficient.

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