Write a VHDL model for an eight-bit register with synchronous enable and reset. As usual, reset has priority over enable.
Hint.
See Listing 8.1.5
Section 8.2 Registers
It is easy to extend the model for a single flip-flop to a multi-bit register.
-- D and Q are previously declared std_logic_vector(7 downto 0)
process(clk)
begin
if rising_edge(clk) then
if CE = '1' then
Q <= D;
end if;
end if;
end process;
Notice that, except for the vector nature of
D and Q, the model is identical to Listing 8.1.2! Including a synchronous reset is equally straightforward.
