Sometimes we need a counter with a step size that can be input via a port or signal. One example is shown in Figure 10.4.1, below. The count, \(X\text{,}\) and the increment, \(\Delta\text{,}\) are \(N\)-bit (unsigned) numbers. The adder lacks both a carry-in and a carry-out; its output is the sum \(X + \Delta\text{,}\) modulo \(2^N\text{.}\) For example, if \(N=4\) and \(\Delta=3\text{,}\) the count sequence will be 0, 3, 6, 9, 12, 15, 2, 5, 8, 11, 14, 1,...
Block diagram
Figure10.4.1.Counter with externally supplied step size.
The VHDL model for this counter is also straightforward.
-- numeric_std library is included.
-- Signals X and delta are previously declared unsigned(N-1 downto 0).
process(clk)
begin
if rising_edge(clk) then
X <= X + delta;
end if;
end process;
Listing10.4.2.VHDL model for an \(N\)-bit counter with external step size.
The basic counter can be embellished in the usual ways, with reset and/or enable, or adding an output signal that detects when the counter has rolled over.
ExercisesExercises
1.Variable-step counter with overflow.
Redesign the variable step-size counter so that it asserts an overflow signal, OV, for one clock cycle when the count rolls over, e.g., from 15 to 2. Draw a block diagram, write a VHDL model from the block diagram, and validate the design through simulation.
