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Section 9.3 A template for mixed synchronous and asynchronous processes
process(clk, A, B, ...) -- 1
begin
if rising_edge(clk) then -- 2
-- synchronous logic
end if;
-- asynchronous logic -- 3
end process;
The sensitivity list includes the clock and all inputs to the asynchronous part.
The synchronous logic is inside the if rising_edge(clk)...end if block.. Every signal assignment in this block is registered (stored in flip-flops).
The asynchronous logic is outside the if rising_edge(clk)...end if block. These signal assignments are not registered.
