Section 6.4 If-then-else statements
The various VHDL models we have seen for the multiplexer are all based on the logic equation or logic diagram. They are all correct, but none of them capture the essence of the multiplexer’s behavior, which is really “if-then-else”. VHDL provides this construction for processes. With it, the multiplexer architecture is:
architecture behavioral of mux2to1 is
begin
mux2: process(A, B, S)
begin
if S='0' then
y <= A;
else
y <= B;
end if;
end process mux2;
end behavioral;
This model expresses the multiplexer’s behavior more directly than the logic equation. Consequently, it is more readable, and in VHDL as in software engineering, readable code is much less prone to bugs. Furthermore, this construction is easily reused in any architecture where a multiplexer appears in the block diagram, without pausing to render the multiplexer into a logic equation.
Another benefit of the if-then-else version of the multiplexer model is that it is easily extended to vector inputs. Suppose you need to select one of two 8-bit bundles. After declaring the two data inputs and the output as
std_logic_vector(7 downto 0), the rest of the model is identical to the single-bit version! (Imagine doing this with logic equations, one for each bit.)Frequently, we want to use nested if-then-else statements, for a hierarchical choice. For example, consider a multiplexer with an enable (EN) bit. When EN is false, the output is "0...0" regardless of what the other inputs are doing. But, if EN is true, then input A or B is selected as usual, based on the value of the select (S) bit. This would be modeled as so:
architecture behavioral of mux2to1_en is
begin
mux2en: process(A, B, S, EN)
begin
if EN='0' then
y <= "00000000"; -- assuming 8-bit vectors
elsif S='0' then
y <= A;
else
y <= B;
end if;
end process mux2en;
end behavioral;
