Processes

Section 6.2 Processes

VHDL models based just on logic equations are straightforward, but very limited. We will now introduce a major feature of the language which enables more complex models to be written with greater ease.

A statement like y <= a and b; represents a series of steps in the simulation of the model:

Wait, suspended, for an event on a port or signal.
When an event occurs, evaluate the statement.
Assign the result and suspend, pending another event.

The statement is, in fact, a shorthand for the central VHDL construct, called a process, that explicitly includes these steps. Here is the basic process syntax:

process              
begin              
   y <= a and b;  -- 2 (evaluate)
   wait on a, b;     -- 3 (assign, suspend)  
                     -- 1 (wait)            
end process;

In simulation the process waits, inactive, pending an event on a or b. When an event occurs, the simulator activates the process and executes the statements, in order. The first one, y <= a and b;, is evaluated. The new value of y is noted, but not assigned. We say that the output is scheduled. When the simulator executes the second statement, wait on a, b;, the scheduled output is assigned, and the process suspends. It then waits for the next event on either input.

The same statement, y <= a and b;, means different things when it stands alone in an architecture and when it is included inside a process:

As a standalone statement, y <= a and b; is shorthand for a process; Waiting, activating, scheduling, assigning, and suspending are all implicit.
Inside a process, y <= a and b; merely schedules the assignment of a new value to y. Suspension, waiting, and activation are made explicit by the wait a, b statement.

A more common way to write a process, which we shall use from now on, is:

process(a, b)                 
begin              
   y <=a and b;              
end process;

The parenthesized list (a, b) is called the sensitivity list for the process. The process is said to be sensitive to a and b. The items in the sensitivity list look like function arguments in a conventional programming language, but they are not and should not be mistaken for such. Rather, the sensitivity list replaces the explicit wait statement in the previous model, naming the ports or signals whose events will activate the process.

Here is the three-statement multiplexer model, written with explicit processes. Like the logic gates they represent, they are concurrent. Each operates only in response to events on its inputs, interacting with other gates / processes only through interconnecting ports and signals.

-- Two-input multiplexer model, gate-by-gate, with processes
   library IEEE;
   use IEEE.std_logic_1164.all;

   entity mux2to1 is
       port( A, B:  in  std_logic;     
             S:     in  std_logic;     
             y:     out std_logic );   
   end mux2to1;

   architecture gatelevel of mux2to1 is
       signal asn, bs: std_logic;      -- intermediate nets
   begin

   and_gate_1: process(A, S)           -- labels are optional, but helpful
      begin
         asn <= not(S) and A;
      end process and_gate_1;

   and_gate_2: process(B, S)
      begin
         bs <= S and B;
      end process and_gate_2;

   or_gate: process(asn, bs)
      begin  
         y <= asn or bs;	 
      end process or_gate;

   end gatelevel;

Listing 6.2.1. Gate-level model for the two-input multiplexer, with each gate represented by a process.

Checkpoint 6.2.2.

Walk through the model in Listing 6.2.1, for events on A, B, and S, making sure you understand the seqence of events and activations leading to the output.

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